Alpha bugs

Updates by: Ilya Wagner and Valeria Bertacco
            The University of Michigan

   Disclaimer: the authors do not warrant or assume any legal liability
   or responsibility for the accuracy, completeness, or usefulness of
   this software, nor for any damage derived by its use.
   
1) regfile.v 
write to zero-reg succeeds if rdb_idx

2)memstage.v
load following store to the same addr produces bad result

3)regfile.v
internal forwarding in rda

4) exstage.v
forwarding through zero reg on rb

5) exstage.v
forwarding from wb instead of mem when both match

6)exstage.v
uncond branch following cond branch with the same imm will not be taken

7)idstage.v
pipeline is stalled when 10 is rda and rdd

8)exstage.v
if dependency between mem and ex on ra and ra=20 then rb is forwarded from wb

9)exstage
cond branch with negative imm after a store to positive address is not taken

10) pipeline
squash if mem_wb ra == id_ex rd and instr in id ex is not any branch